riscv
for embedded developers, compiler engineers
Why this scored 2
every term, weightedIts fastest-moving item, measured against the pace of its own source
Whether that velocity is itself speeding up, as a per-hour rate
How many independent communities its own items come from
Decays to zero over 14 days, counted from when we first saw it
Subtracted once something is big and old — sized by its biggest item, aged from when we first saw it
Weights are hand-tuned, not learned — we're calibrating them against realized trends as history accumulates. On an entity's first sighting there's no previous reading to compare against, so acceleration starts from a neutral prior rather than a measurement, and velocity falls back to engagement over its whole lifetime until a second reading exists. Full methodology
Signal history
7-day window (free)The evidence
The live items this entity's score aggregates — every community independently talking about it right now. This is the corroboration, shown, not claimed.
- 175
A Third World Embedded Engineer Responds to "RISC-V: They Should Have Known Better"
RISC-V debate highlights accessibility concerns for embedded engineers. · for embedded engineers
lobstersPeaking 2 · riscvhardware25d ago - 234
RISC-V interpreter from the future
A Rust-based RISC-V interpreter lets developers test low-level code without hardware. · for embedded developers, compiler engineers
lobstersSteady 3 · rustdevtools9d ago - 333
RISC-V: They Should Have Known Better
Discusses recent RISC-V developments and missed opportunities. · for hardware architects
lobstersSteady 2 · riscvhardware27d ago - 428
Hot Chips 2026: CUDA targets RISC-V
CUDA adding RISC-V support expands GPU compute to open-source hardware. · for gpu developers, hardware engineers
lobstersSteady 2 · cudahardware17d ago - 528
RISC-V: They Should Have Known Better
RISC-V ecosystem shifts may affect chip design choices and tool support. · for chip designers, hardware engineers
hackernewsSteady 2 · riscvhardware26d ago - 617
Hot Chips 2026: CUDA Targets RISC-V – By Chester Lam
CUDA adds support for RISC-V, expanding GPU acceleration to open-source CPU architectures. · for chip designers
hackernewsSteadyhardware17d ago - 716
Show HN: A Project Oberon System version running on RISC-V instead of RISC-5
RISC-V runs Project Oberon · for hardware engineers
hackernewsSteadyhardware32d ago - 816
RISC-V: They should have known better
RISC-V ecosystem faces criticism that may affect future chip design choices. · for chip designers
hackernewsSteadyhardware27d ago - 915
A third world engineer responds to “RISC-V: They should have known better”
Highlights criticism of RISC-V adoption that could affect hardware roadmap decisions. · for chip designers
hackernewsSteadyhardware25d ago - 1012
Comu Fits a 144MHz CH32V203 RISC-V Board Inside a USB-A Port
RISC-V board in USB · for hardware engineers
lobstersSteadyhardware36d ago - 119
RISC-V Is Inevitable: State of the Union Keynote Argues
RISC-V is inevitable · for hardware engineers
hackernewsSteady 2 · riscvhardware56d ago - 125
RISC-V return address corruption bug
RISC-V return address bug · for fpga devs
stackoverflowSteadyhardware57d ago