riscv
for formal methods researchers, kernel engineers
Why this scored 24
every term, weightedIts fastest-moving item, measured against the pace of its own source
Whether that velocity is itself speeding up, as a per-hour rate
How many independent communities its own items come from
Decays to zero over 14 days, counted from when we first saw it
Subtracted once something is big and old — sized by its biggest item, aged from when we first saw it
Weights are hand-tuned, not learned — we're calibrating them against realized trends as history accumulates. On an entity's first sighting there's no previous reading to compare against, so acceleration starts from a neutral prior rather than a measurement, and velocity falls back to engagement over its whole lifetime until a second reading exists. Full methodology
Signal history
7-day window (free)The evidence
The live items this entity's score aggregates — every community independently talking about it right now. This is the corroboration, shown, not claimed.
- 175
A Third World Embedded Engineer Responds to "RISC-V: They Should Have Known Better"
RISC-V debate highlights accessibility concerns for embedded engineers. · for embedded engineers
lobstersPeaking 2 · riscvhardware70d ago - 238
Extending concurrent separation logic to the hardware level to verify the xv6 OS kernel on RISC-V with AI agents
Applies AI-augmented separation logic to verify the xv6 kernel on RISC-V hardware. · for formal methods researchers, kernel engineers
lobstersEmergingdevtools4d ago - 334
Show HN: Our space game has a built-in RISC-V emulator that runs Linux
Built-in RISC-V emulator runs Linux inside the game, enabling low-level experimentation. · for game developers, system programmers
hackernewsSteady 3 · linuxhardware21d ago - 434
RISC-V interpreter from the future
A Rust-based RISC-V interpreter lets developers test low-level code without hardware. · for embedded developers, compiler engineers
lobstersSteady 3 · rustdevtools54d ago - 533
RISC-V: They Should Have Known Better
Discusses recent RISC-V developments and missed opportunities. · for hardware architects
lobstersSteady 2 · riscvhardware72d ago - 628
Hot Chips 2026: CUDA targets RISC-V
CUDA adding RISC-V support expands GPU compute to open-source hardware. · for gpu developers, hardware engineers
lobstersSteady 2 · cudahardware62d ago - 728
RISC-V: They Should Have Known Better
RISC-V ecosystem shifts may affect chip design choices and tool support. · for chip designers, hardware engineers
hackernewsSteady 2 · riscvhardware71d ago - 818
Our RISC-V emulator PasRISCV
PasRISCV provides a lightweight RISC-V emulator for game and virtualization projects. · for emulator developers, game devs
lobstersSteadydevtools22d ago - 917
Hot Chips 2026: CUDA Targets RISC-V – By Chester Lam
CUDA adds support for RISC-V, expanding GPU acceleration to open-source CPU architectures. · for chip designers
hackernewsSteadyhardware62d ago - 1016
Show HN: A Project Oberon System version running on RISC-V instead of RISC-5
RISC-V runs Project Oberon · for hardware engineers
hackernewsSteadyhardware77d ago - 1116
RISC-V: They should have known better
RISC-V ecosystem faces criticism that may affect future chip design choices. · for chip designers
hackernewsSteadyhardware72d ago - 1215
A third world engineer responds to “RISC-V: They should have known better”
Highlights criticism of RISC-V adoption that could affect hardware roadmap decisions. · for chip designers
hackernewsSteadyhardware70d ago - 1312
Comu Fits a 144MHz CH32V203 RISC-V Board Inside a USB-A Port
RISC-V board in USB · for hardware engineers
lobstersSteadyhardware81d ago - 149
RISC-V Is Inevitable: State of the Union Keynote Argues
RISC-V is inevitable · for hardware engineers
hackernewsSteady 2 · riscvhardware101d ago - 155
RISC-V return address corruption bug
RISC-V return address bug · for fpga devs
stackoverflowSteadyhardware102d ago